This invention relates to a memory cell configuration for non-volatile memory arrays.
Fabrication of high density non-volatile memory cells with a stacked floating gate arrangement requires additional processing steps as compared to the fabrication of standard logic CMOS devices. As a result, the fabrication process for non-volatile memory cells typically lags behind the leading process technology available for the fabrication of logic CMOS devices. For example, the leading logic CMOS process in 2010 has been at the 28 nm process level, whereas the most advanced process technology for high-density non-volatile memory embedded in CMOS has been based on a 90 nm process.
It is possible to fabricate low density non-volatile memory arrays using standard CMOS processes without any additional process steps by abandoning the stacked gate arrangement. This can be achieved by, for example, attaching a coupling capacitor, sensing transistor and tunnelling capacitor to different active regions defined in a semiconductor substrate beneath a common floating gate electrode. Such a cell structure is described in U.S. Pat. No. 7,671,401 and is illustrated in FIG. 1. In FIG. 1, 23 represents a programming transistor, 21 represents an access transistor and 22 represents a control capacitor.
However, such low density non-volatile memory cells have the disadvantage that the area consumed by each memory cell is large as compared with more conventional high-density non-volatile memory cells. This is a result of having to ensure that the active regions of the memory cell are sufficiently well-spaced in the substrate to avoid interaction between the component parts of the cell. This is true even for non-volatile memories having a common floating gate electrode that make use of more advanced process technology. For example, non-volatile memory having a common floating gate electrode (NOVeA) is available from Synopsys that is fabricated using 65 nm process technology, but estimates indicate that these devices still require an area of around 40 um2 per bit. See Rosenberg, John; “Embedded Flash on Standard CMOS Logic Enables Security for Deep Submicron Designs”; Virage Logic s.l.; Government Microcircuit Applications Critical Technology Conference, 2009.
Furthermore, the general pursuit of non-volatile memory cells using deep submicron CMOS technologies with no added process steps is hampered by charge loss from the floating electrode by Frenkel-Poole conduction. Such charge loss is caused by the use of non-stoichiometric dielectric layers over the gate stack in order to provide etch-stop layers and control the mechanical stress so as to enhance the mobility of the CMOS channel. The charge loss is exacerbated when the gate stack height and spacer width is reduced. Moving to a low density memory cell structure increases the likelihood of charge loss by Frenkel-Poole conduction due to the large relative perimeter of the separate coupling capacitor.
There is therefore a desire for higher-density non-volatile memory cells that can be entirely fabricated using standard CMOS processing steps. This would allow non-volatile memory cells to access leading CMOS process technologies and hence leverage the benefits of smaller size, higher speed and lower power consumption provided by improved process technology. Additionally, there is a need to address the charge loss in nanoscale non-volatile memory cells due to Frenkel-Poole conduction.